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MC74AC109, MC74ACT109 Dual JK Positive Edge-Triggered Flip-Flop
The MC74AC109/74ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip-flop (refer to MC74AC74/74ACT74 data sheet) by connecting the J and K inputs together. Asynchronous Inputs: LOW input to SD (Set) sets Q to HIGH level LOW input to CD (Clear) sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on CD and SD makes both Q and Q HIGH
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16 1
DIP-16 N SUFFIX CASE 648
* Outputs Source/Sink 24 mA * ACT109 Has TTL Compatible Inputs
VCC 16 CD2 15
CD
16 Q2 10
Q Q
J2 14
J
K2 13
K
CP2 12
CP
SD2 11
SD
Q2 9 16
1
SO-16 D SUFFIX CASE 751B
1
TSSOP-16 DT SUFFIX CASE 948F
CD1 J1
K1
CP1
SD1
Q1
Q1
1 CD1
2 J1
3 K1
4 CP1
5 SD1
6 Q1
7 Q1
8 GND
16 1
EIAJ-16 M SUFFIX CASE 966
Figure 1. Pinout; 16-Lead Packages Conductors (Top View) PIN ASSIGNMENT
PIN J1, J2, K1, K2 CP1, CP2 CD1, CD2 SD1, SD2 Q1, Q2, Q1, Q2 FUNCTION Data Inputs Clock Pulse Inputs Direct Clear Inputs Direct Set Inputs Outputs
ORDERING INFORMATION
Device MC74AC109N MC74ACT109N MC74AC109D MC74ACT109D MC74AC109DR2 MC74ACT109DR2 MC74AC109DT MC74ACT109DT MC74AC109DTR2 Package PDIP-16 PDIP-16 SOIC-16 SOIC-16 SOIC-16 SOIC-16 TSSOP-16 TSSOP-16 Shipping 25 Units/Rail 25 Units/Rail 48 Units/Rail 48 Units/Rail 2500 Tape & Reel 2500 Tape & Reel 96 Units/Rail 96 Units/Rail
TSSOP-16 2500 Tape & Reel
MC74ACT109DTR2 TSSOP-16 2500 Tape & Reel MC74AC109M MC74ACT109M MC74AC109MEL MC74ACT109MEL EIAJ-16 EIAJ-16 EIAJ-16 EIAJ-16 50 Units/Rail 50 Units/Rail 2000 Tape & Reel 2000 Tape & Reel
DEVICE MARKING INFORMATION
See general marking information in the device marking section on page 6 of this data sheet.
(c) Semiconductor Components Industries, LLC, 2001
1
May, 2001 - Rev. 5
Publication Order Number: MC74AC109/D
MC74AC109, MC74ACT109
TRUTH TABLE
Inputs SD L H L H H H H H CD H L L H H H H H CP X X X J X X X L H L H X K X X X L L H H X Outputs Q H L H L Q SD Q J CP Q K CD
L
L H H H Toggle Q0 Q0- H L Q0 Q0-
SD
Q J CP
Q K
CD
H = HIGH Voltage Level L = LOW Voltage Level = LOW-to-HIGH Clock Transition X = Immaterial Q0(Q0) = Previous Q0(Q0) before LOW-to-HIGH Transition of Clock
Figure 2. Logic Symbol
SD
K
Q
CP Q
J
CD NOTE: This diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Figure 3. Logic Diagram (One Half Shown)
MAXIMUM RATINGS*
Symbol VCC VIN VOUT IIN IOUT ICC Tstg Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Sink/Source Current, per Pin DC VCC or GND Current per Output Pin Storage Temperature Value -0.5 to +7.0 -0.5 to VCC +0.5 -0.5 to VCC +0.5 20 50 50 -65 to +150 Unit V V V mA mA mA C
*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions.
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MC74AC109, MC74ACT109
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VIN, VOUT Supply Voltage DC Input Voltage, Output Voltage (Ref. to GND) VCC @ 3.0 V tr, tf Input Rise and Fall Time (Note 1) AC Devices except Schmitt Inputs VCC @ 4.5 V VCC @ 5.5 V tr, tf TJ TA IOH IOL In ut Input Rise and Fall Time (Note 2) ACT Devices except Schmitt Inputs Junction Temperature (PDIP) Operating Ambient Temperature Range Output Current - High Output Current - Low VCC @ 4.5 V VCC @ 5.5 V Parameter AC ACT Min 2.0 4.5 0 - - - - - - -40 - - Typ 5.0 5.0 - 150 40 25 10 8.0 - 25 - - Max 6.0 5.5 VCC - - - - ns/V - 140 85 -24 24 C C mA mA ns/V V V Unit
1. VIN from 30% to 70% VCC; see individual Data Sheets for devices that differ from the typical input rise and fall times. 2. VIN from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times.
DC CHARACTERISTICS
74AC Symbol Parameter VCC (V) TA = +25C Typ VIH Minimum High Level g Input Voltage Maximum Low Level Input Voltage Minimum High Level g Output Voltage 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 VOL Maximum Low Level Output Voltage 3.0 4.5 5.5 3.0 4.5 5.5 IIN IOLD IOHD ICC Maximum Input Leakage Current Minimum Dynamic Output C O t t Current t Maximum Q Quiescent Supply Current 5.5 55 5.5 5.5 5.5 55 1.5 2.25 2.75 1.5 2.25 2.75 2.99 4.49 5.49 - - - 0.002 0.001 0.001 - - - - - - - 74AC TA = -40C to +85C Unit Conditions
Guaranteed Limits 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 2.56 3.86 4.86 0.1 0.1 0.1 0.36 0.36 0.36 0.1 0 1 - - 4.0 40 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 2.46 3.76 4.76 0.1 0.1 0.1 0.44 0.44 0.44 1.0 1 0 75 -75 40 V VOUT = 0.1 V or VCC - 0.1 V VOUT = 0.1 V or VCC - 0.1 V IOUT = -50 A V *VIN = VIL or VIH -12 mA IOH -24 mA -24 mA IOUT = 50 A V *VIN = VIL or VIH 12 mA IOL 24 mA 24 mA VI = VCC, GND VOLD = 1.65 V Max VOHD = 3.85 V Min VIN = VCC or GND
VIL
V
VOH
V
V
A mA mA A
*All outputs loaded; thresholds on input associated with output under test. Maximum test duration 2.0 ms, one output loaded at a time. NOTE: IIN and ICC @ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V VCC.
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MC74AC109, MC74ACT109
AC CHARACTERISTICS (For Figures and Waveforms - See Section 3 of the ON Semiconductor FACT Data Book, DL138/D)
74AC Symbol Parameter VCC* (V) Min fmax tPLH tPHL tPLH tPHL Maximum Clock Frequency Propagation Delay g y CPn to Qn or Qn Propagation Delay g y CPn to Qn or Qn Propagation Delay g y CDn or SDn to Qn or Qn Propagation Delay g y CDn or SDn to Qn or Qn 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 125 150 4.0 2.5 3.0 2.0 3.0 2.5 3.0 2.0 TA = +25C CL = 50 pF Typ - - - - - - - - - - Max - - 13.5 10.0 14.0 10.0 12.0 9.0 12.0 9.5 74AC TA = -40C to +85C CL = 50 pF Min 100 125 3.5 2.0 3.0 1.5 2.5 2.0 3.0 2.0 Max - - 16.0 10.5 14.5 10.5 13.0 10.0 13.5 10.5 MHz ns ns ns ns 3-3 3-6 3-6 3-6 3-6 Unit Fig. No.
*Voltage Range 3.3 V is 3.3 V 0.3 V. *Voltage Range 5.0 V is 5.0 V 0.5 V.
AC OPERATING REQUIREMENTS
74AC Symbol Parameter VCC* (V) Typ ts th tw trec Set u Set-up Time, HIGH or LOW Jn or Kn to CPn Hold Time, HIGH or LOW Jn or Kn to CPn Pulse Width CPn or CDn or SDn Recovery TIme CDn or SDn to CP 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 - - - - - - - - TA = +25C CL = 50 pF 74AC TA = -40C to +85C CL = 50 pF Unit Fig. No.
Guaranteed Minimum 6.5 4.5 0 0.5 4.0 3.5 0 0 7.5 5.0 0 0.5 4.5 3.5 0 0 ns ns ns ns 3-9 3-9 3-6 3-9
*Voltage Range 3.3 V is 3.3 V 0.3 V. *Voltage Range 5.0 V is 5.0 V 0.5 V.
DC CHARACTERISTICS
74ACT Symbol Parameter VCC (V) TA = +25C Typ VIH VIL VOH Minimum High Level g Input Voltage Maximum Low Level Input Voltage Minimum High Level g Output Voltage 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 1.5 1.5 1.5 1.5 4.49 5.49 - - 74ACT TA = -40C to +85C Unit Conditions
Guaranteed Limits 2.0 2.0 0.8 0.8 4.4 5.4 3.86 4.86 2.0 2.0 0.8 0.8 4.4 5.4 3.76 4.76 V V V VOUT = 0.1 V or VCC - 0.1 V VOUT = 0.1 V or VCC - 0.1 V IOUT = -50 A *VIN = VIL or VIH -24 mA IOH -24 mA
V
*All outputs loaded; thresholds on input associated with output under test. Maximum test duration 2.0 ms, one output loaded at a time.
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MC74AC109, MC74ACT109
DC CHARACTERISTICS (continued)
74ACT Symbol Parameter VCC (V) TA = +25C Typ VOL Maximum Low Level Output Voltage 4.5 5.5 4.5 5.5 IIN ICCT IOLD IOHD ICC Maximum Input Leakage Current Additional Max. ICC/Input Minimum Dynamic Output C O t t Current t Maximum Q Quiescent Supply Current 5.5 55 5.5 5.5 5.5 5.5 55 0.001 0.001 - - - 0.6 - - - 74ACT TA = -40C to +85C Unit Conditions
Guaranteed Limits 0.1 0.1 0.36 0.36 0.1 0 1 - - - 4.0 40 0.1 0.1 0.44 0.44 1.0 1 0 1.5 75 -75 40 V IOUT = 50 A *VIN = VIL or VIH 24 mA IOL 24 mA VI = VCC, GND VI = VCC - 2.1 V VOLD = 1.65 V Max VOHD = 3.85 V Min VIN = VCC or GND
V
A mA mA mA A
*All outputs loaded; thresholds on input associated with output under test. Maximum test duration 2.0 ms, one output loaded at a time.
AC CHARACTERISTICS (For Figures and Waveforms - See Section 3 of the ON Semiconductor FACT Data Book, DL138/D)
74ACT Symbol Parameter VCC* (V) Min fmax tPLH Maximum Clock Frequency 5.0 50 5.0 50 5.0 50 5.0 50 5.0 50 145 4.0 40 3.0 30 2.5 25 2.5 25 TA = +25C CL = 50 pF Typ - - - - - Max - 11.0 11 0 10.0 10 0 9.5 95 10.0 10 0 74ACT TA = -40C to +85C CL = 50 pF Min 125 3.5 35 2.5 25 2.0 20 2.0 20 Max - 13.0 13 0 11.5 11 5 10.5 10 5 11.5 11 5 MHz ns ns ns ns 3-3 3-6 3-6 3-6 3-6 Unit Fig. No.
Pro agation Propagation Delay CPn to Qn or Qn Pro agation Propagation Delay tPHL CPn to Qn or Qn Pro agation Propagation Delay tPLH CDn or SDn to Qn or Qn Pro agation Propagation Delay tPHL CDn or SDn to Qn or Qn *Voltage Range 5.0 V is 5.0 V 0.5 V.
AC OPERATING REQUIREMENTS
74ACT Symbol Parameter VCC* (V) Typ Set u Set-up Time, HIGH or LOW Jn or Kn to CPn Hold Time, HIGH or LOW th Jn or Kn to CPn Pulse Width tw CPn or CDn or SDn *Voltage Range 5.0 V is 5.0 V 0.5 V. ts 5.0 50 5.0 50 5.0 50 - - - TA = +25C CL = 50 pF 74ACT TA = -40C to +85C CL = 50 pF Unit Fig. No.
Guaranteed Minimum 2.0 20 2.0 20 5.0 50 2.5 25 2.0 20 6.0 60 ns ns ns 3-9 3-9 3-6
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MC74AC109, MC74ACT109
AC OPERATING REQUIREMENTS (continued)
74ACT Symbol Parameter VCC* (V) Typ Recovery TIme CDn or SDn to CP *Voltage Range 5.0 V is 5.0 V 0.5 V. trec 5.0 50 - TA = +25C CL = 50 pF 74ACT TA = -40C to +85C CL = 50 pF Unit Fig. No.
Guaranteed Minimum 0 0 ns 3-9
CAPACITANCE
Symbol CIN CPD Input Capacitance Power Dissipation Capacitance Parameter Value Typ 4.5 35 Unit pF pF Test Conditions VCC = 5.0 V VCC = 5.0 V
MARKING DIAGRAMS
DIP-16 MC74AC109N AWLYYWW SO-16 AC109 AWLYWW TSSOP-16 EIAJ-16
AC 109 ALYW
74AC109 ALYW
MC74ACT109N AWLYYWW
ACT109 AWLYWW
ACT 109 ALYW
74ACT109 ALYW
A WL, L YY, Y WW, W
= Assembly Location = Wafer Lot = Year = Work Week
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MC74AC109, MC74ACT109
PACKAGE DIMENSIONS
PDIP-16 N SUFFIX 16 PIN PLASTIC DIP PACKAGE CASE 648-08 ISSUE R
9
-A-
16
B
1 8
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01
F S
C
L
-T- H G D
16 PL
SEATING PLANE
K
J TA
M
M
0.25 (0.010)
M
SO-16 D SUFFIX 16 PIN PLASTIC SOIC PACKAGE CASE 751B-05 ISSUE J
-A-
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019
-B-
1 8
P
8 PL
0.25 (0.010)
M
B
S
G F
K C -T-
SEATING PLANE
R
X 45 _
M D
16 PL M
J
0.25 (0.010)
TB
S
A
S
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MC74AC109, MC74ACT109
PACKAGE DIMENSIONS
TSSOP-16 DT SUFFIX 16 PIN PLASTIC TSSOP PACKAGE CASE948F-01 ISSUE O
16X K REF
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V
S
K K1
16
2X
L/2
9
J1 B -U-
L
PIN 1 IDENT. 1 8
SECTION N-N J
N 0.15 (0.006) T U
S
0.25 (0.010) M
A -V- N F DETAIL E
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
C 0.10 (0.004) -T- SEATING
PLANE
H D G
DETAIL E
EIAJ-16 M SUFFIX 16 PIN PLASTIC EIAJ PACKAGE CASE966-01 ISSUE O
16 9
LE Q1 E HE M_ L DETAIL P
1
8
Z D e A VIEW P
b 0.13 (0.005)
M
A1 0.10 (0.004)
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EEE CCC EEE CCC
c
-W-
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX --2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 0_ 10 _ 0.70 0.90 --0.78 INCHES MIN MAX --0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 0_ 10 _ 0.028 0.035 --0.031
MC74AC109, MC74ACT109
Notes
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MC74AC109, MC74ACT109
Notes
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MC74AC109, MC74ACT109
Notes
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MC74AC109, MC74ACT109
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MC74AC109/D

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